1. Field of the Invention
The invention is directed to the mass production of semiconductor devices. The invention is more particularly directed to the problem of perceiving interactions between interrelated process steps on a mass-production line and maintaining acceptable critical dimensions across each die of a plurality of mass-produced integrated circuit wafers.
2. Cross Reference to Related Publications
The following publications are cited here for purposes of reference:
(1) S. Kaplan and L. Karklin, "Calibration of Lithography Simulator by Using Substitute Patterns," Proceedings on Optical/Laser Microlithography VI, SPIE 1927, pp847-858, 1993. PA1 (2) C. Mack and E. Charrier, "Yield Modeling for Photolithography," Proceedings of OCG Microlithography Seminar, pp171-182, 1994. PA1 (3) TMA DEPICT, Two-Dimensional Process Simulation Program for Deposition, Etching, and Photolithography, version 3.0, Technology Modeling Associates, Inc., Palo Alto, Calif., 1993. PA1 (4) Mandel, J, The Statistical Analysis of Experimental Data, chapter 12. Wiley, New York, 1964 PA1 (5) Z. Krivokapic and W. D. Heavlin, "Predicting Manufacturing Variabilities for Deep micron Technologies: Integration of Process, Device, and Statistical Simulations," in Simulation of Semiconductor Devices and Processes, 5, S. Selberherr, H. Stippel and E. Strasser, eds, pp229-232, Springer-Verlag, New York, 1993. PA1 (6) W. D. Heavlin and G. P. Finnegan, "Dual Space Algorithms for Designing Space-filling Experiments," Interface 1994, Research Triangle, N.C., June 1994. PA1 (7) B. D. Ripley, Spatial Statistics, pp44-75, Wiley, New York, 1981. PA1 (8) A. B. Owen, "Controlling Correlations in Latin Hypercube Samples," Journal of the American Statistical Association, vol 89, no. 428, pp1517-1522, December 1994. PA1 (9) W. D. Heavlin, "Variance Components and Computer Experiments," 1994 ASA Proceedings, section on Physical and Engineering Sciences, Toronto, August 1994. PA1 (10) A. R. Neureuther and F. H. Dill, "Photoresist Modeling and Device Fabrication Applications," Optical and Acoustical Microelectronics, pp223-247, Polytechnic Press, New York, 1974. PA1 (11) F. H. Dill, J. A. Tuttle, A. R. Neureuther, "Modeling Positive Photoresist," Proceedings, Kodak Microelectronics Seminar, pp24-31, 1974. PA1 (12) C. Mac, "Development of Positive Photoresists," Journal of the Electrochemical Society, vol 134, January 1987. PA1 (13) M. Stein, "Large Sample Properties of Simulations using Latin Hypercube Sampling," Technometrics, vol 29, no 2, pp143-151, May 1987. PA1 (14) M. D. McKay and R. J. Beckman, "Using Variance to Identify Important Inputs," 1994 ASA Proceedings, Section on Physical and Engineering Sciences, Toronto, August 1994. PA1 (a) taking sample measurements of critical dimensions for a given test feature (e.g., in-scribe first-poly linewidths) within the outflow of a mass production line; PA1 (b) developing a statistical profile of the sampled measurements; PA1 (c) extrapolating from the sample profile a broader statistical profile that applies to other features (e.g., within-die poly linewidths) of the production line outflow; PA1 (d) comparing the extrapolated statistical profile against a predefined acceptable profile; and PA1 (e) consulting a computer-implemented process model to select and adjust those process steps that will most quickly bring the extrapolated profile into agreement with the acceptable profile.
3. Description of the Related Art
Modern, high-density, integrated circuit devices are typically mass-produced with large numbers of critically-dimensioned features.
Examples of critically-dimensioned (CD) features include transistor channel length (gate length), transistor channel width, trench depth, step slope, and so forth.
The channel length ,of each insulated gate field effect transistor (IGFET) within an integrated circuit is critical for example, because the length determines a variety of local and global characteristics such as maximum transistor switching speed, overall device operating speed, overall power consumption, breakdown voltage, and so forth. The combination of gate length and channel width defines the area consumed by each transistor. The pitch and other dimensional values of repeated structures establish the maximum packing density for multiple circuits within an integrated circuit (IC) die having given maximum dimensions.
It is desirable to maintain the respective critical dimensions of each die within a plurality of mass-produced IC wafers constrained to certain respective value ranges (or `guard bands`) in order to assure desired operating speeds and other dimension-dependent characteristics.
Ideally, every device produced by a given mass production line should have the same critical dimensions for each of its transistors and/or each of its other basic electronic components (e.g., resistors, capacitors, interconnect lines).
The reality, however, is that the critical dimensions of mass-produced devices are subject to small, but nonetheless significant, random variations.
Random variations tend to occur between the critical dimensions of one mass-produced wafer and the next. Random variations tend to occur between the critical dimensions of one IC chip and the next as one sweeps across a given wafer. Random variations tend to occur even between the critical dimensions of one transistor and the next as one sweeps across a given integrated circuit (IC) chip or `die` of a mass-produced wafer. The variations across a given die are sometimes referred to as cross-reticle deviation.
Each feature on each IC die in a mass-produced wafer is the product of a succession of many process steps. Each process step is controlled by a combination of variable process parameters.
Different combinations of variations in process parameter can occur on a random basis across the plural process steps of amass-production line, on a die-by-die basis. This introduces `noise` into the uniformity of the product outflow of the mass-production line. Sometimes a specific permutated-combination of process parameter deviations is relatively innocuous, sometimes it is not. It all depends on which process parameters are deviated for a given IC die and how their respective process steps interrelate to establish critical dimensions on that given die.
By way of example, consider the multiple, interrelated process steps that are typically employed to define a pattern of conductive lines disposed across an insulator of an IC chip.
First, a dielectric layer of a generally non-planar form is created across the wafer. Such a non-planar dielectric layer may constitute the combined gate oxide and field oxide of a CMOS device. The non-planarity of the dielectric layer may alternatively be attributed to the non-planarity of underlying trenches, steps, mesas or other topographic features of the chip.
Next, a polysilicon or other conductive layer is deposited conformably on top of the dielectric layer. An anti-reflective coating (ARC) may be optionally deposited on the conductive layer to reduce undesired reflections in a following exposure step.
The deposition of the conductive layer and optional ARC layer is followed by a spinning-on or other deposition of a photoresist (PR) layer. The PR layer may or may not be planarized depending on process specifics.
The photoresist-coated wafer is then positioned within a stepper by an alignment mechanism. Tiled areas of the photoresist (PR) are successively exposed to a stepped pattern of resist-modifying radiation. After the step-wise exposure, the photoresist is "developed" by, for example, soft baking the wafer to induce cross-polymerization in the photoresist material and by subsequently dissolving away non-hardened portions of the photoresist with a specific solvent. The developed photoresist defines an etch mask.
The developed wafer is next etched, for example in a plasma etch chamber, so as to transfer the hardened image in the photoresist to the conductive layer. This produces a corresponding pattern of lines in the conductive (e.g., doped polysilicon) layer.
The photoresist mask is stripped off, or kept depending on process specifics, and further process steps follow. One example of a further process step is the selective implant of dopants into exposed semiconductor regions so as to create self-aligned source and drain regions at opposed sides of each conductive line, where the conductive line lies over gate oxide. The width of the conductive line at such a region of dopant implant defines the channel length of the formed IGFET transistor.
Within each of the above-described process steps, there are one or more variable physical attributes (or `process parameters`) that control the final outcome. Some process parameters may be adjusted by a line operator. Some are `set` by the design of the process equipment that is installed into the mass-production line.
Irrespective of how and when an attempt is made to `set` each process parameter to a particular goal value (either while the mass-production line is up and running, or when new production equipment is introduced into the mass-production line), the `setting` does not always define precisely what the actual value of the process parameter will be during any given instant of line operation for a given IC die. There is slack in virtually every setting. The actual value of each `pre-set` process parameter can drift or otherwise move away from its goal value due to a variety of mechanisms occurring at different times along the mass-production line.
The over-time variations of process parameters introduce `noise` into the critical dimensions of features (e.g., conductor linewidths, channel length) that define the operating characteristics of the end products flowing off the fabrication line.
An example of noise introduction may be seen by considering the respective thicknesses of the above-mentioned ARC (anti-reflective coating) layer and PR (photoresist) layer. The thicknesses of each may be `set` to respective goal value at the start of a process run. The actual thickness values for the ARC and PR layers may change across a production run, however, due to slight variations in material viscosity, due to different coating adhesion attributes present at the center and edge portions of each wafer, and for a variety of other reasons.
During the radiation exposure step, as one samples individual IC chips of each successive wafer, the position of the radiation pattern focal points may change relative to the photoresist layer. The amount and phase of undesired reflection may change. Such variations may be due to the previously-introduced variations in the respective thicknesses of the ARC and PR layers.
The position and intensity of the radiation pattern relative to the photoresist layer may also change as a consequence of further variance in the exposure optics (e.g., focus drift). Exposure time and dosage may vary from pre-set goal levels on a die-by-die basis. The critical dimensions of radiation-modifying features within the exposure mask may also vary on a die-to-die basis as a result of thermally-driven expansion and contraction.
Consequently, no two randomly-sampled dice on a given wafer are guaranteed to have exactly the same radiation exposure conditions.
Post-exposure development time and temperature are also subject to variance away from pre-established goal values. The diffusion length of the development chemistry may vary across a wafer. In a subsequent plasma etch, the variables can include: time, pressure, temperature, flow rate, and field-proximity effects resulting from the pitch and step profile of closely spaced mask features.
Because successive steps of IC production tend to be interdependent, a slight variation in parameter(s) of one process step can be magnified by a further variation in the parameters of a second process step to produce unacceptable numbers of defective product at the output end of the mass-production line.
For example, if PR (photoresist) thicknesses decreases slightly and the focal depth of the exposure optics also decreases slightly and the exposure dosage also decreases slightly during production of a first-sampled IC chip as compared to the corresponding process parameters for a second-sampled IC chip, the combined effect may be to significantly shift the position and intensity of the radiation exposure pattern relative to the photoresist layer during the production of the first-sampled IC chip. The second-sampled IC chip may come off the production line in acceptable form while the first-sampled chip comes out of the same mass-production line in defective form.
It is hard to pinpoint why mass-production yield for a given circuit layout on a given mass-production line becomes unacceptably low. The statistical variance of PR thickness across the production lot may be small. The statistical variance of focus across the production lot may be small. But the physical interaction between the two noise quantities can be such that the over all lithography process produces chips having a much larger variance in terms of critical dimensions. If the overall variance in final critical dimensions becomes too large, production yield may suffer significantly.
The statistics-wise interdependence of specific process steps is not easily perceived. It is not consistent across all steps, or even as between different product designs. By way of example, compare the layout of a densely packed memory circuit against the less regular layout of a random logic circuit. Some circuit layouts give rise to more so-called `field proximity effects` than others. (Field proximity effects occur in process steps such as exposure and plasma etch.) These field proximity effects can affect mass-production yield, as can many other factors.
In short, a fairly complex matrix of relationships exists between material deposition operations, mechanical operations, optical operations, thermal operations, chemical reactions and the specific layout of each product. It can turn out for each given layout that relatively small variances in certain, key process parameters have far more dominant effects on critical dimensions of the final product than do larger variances in other process parameters.
Heretofore, there was no easy way to perceive for each given circuit layout and the specific process steps that are used to mass-produce that circuit, what contribution the individual variance of each process step made to overall process variance.
Heretofore, when critical dimensions in the outflow of a mass-production line were observed to have slipped out of acceptable range, or were observed to be slipping towards such an undesirable condition, there was no well-defined systematic methodology for determining which process parameters did or did not need adjustment so as to rectify the situation.
If the linewidths in the gate polysilicon layer of mass-produced dice are observed to be coming out too large or too small, should the exposure dosage be adjusted? And if so, in which direction and by how much? Should the line operator play around with the stepper focus first or would it be better to first alter the development time?
Each such situation was dealt with in the past on the basis of gut intuition and trial-and-error guess work. There were simply too many combinations and permutations of process variables to play with.
Production line designers and workers were left to sheer speculation on the root cause when something went wrong in the final output of the mass-production line. Do any of the process variables need to be tweaked? And if so, which process parameter should be adjusted and which should be left alone? Of those that need tweaking, what is the best incremental value for each tweak, and in which direction should it go? If multiple process parameters are to be adjusted, which should be tweaked first?
The problem of figuring out which process parameters need to be tweaked first and by how much, is not limited to pre-established fabrication lines.
It also ripples into the construction plans of next-generation fabrication plants. If one wishes to scale down a given circuit layout from say 0.50 micron linewidths to say, 0.35 micron linewidths, or to 0.20.mu. linewidths, which process parameters are going to require the tightest tolerances? Should the thermal expansion specifications for the exposure mask be tighter than before, or does the key bottleneck to acceptable yields from next-generation fabrication lie in the precision of the optics focus, or in the variance of the development chemistry?
Ideally, one could try to obtain tighter tolerances in all the process steps of the production line. Unfortunately, in the real world, there are finite costs associated with tightening the tolerances of each process step. There are limited budgets in terms of time and resources. Choices have to be made as to which process parameters in a next-generation production line need maximum effort and which do not.
Heretofore, such choices for next-generation plant design and construction were made on a speculative basis. This sometimes led to great waste of time and resources.
Accordingly, there is need within the industry for a more disciplined methodology of quickly and automatically identifying the specific process steps whose noise-induced variations contribute most to problems in the mass-production outflow. There is need within the industry for an automated system of adjusting those process parameters in amass-production line whose adjustment will be most beneficial while leaving alone those whose adjustment will be detrimental.